################################
# setup and proc
# ##############################
source -e -v user_scripts/global_setup.tcl
source -e -v user_scripts/block_setup.tcl
source -e -v user_scripts/loadInnovus.tcl

set current_step "import"

set report_dir "reports/${current_step}"
if {![file exist $report_dir]} {file mkdir $report_dir}

#####################################
# create library
# ##################################
if {[file exists $DESIGN_LIBRARY]} {
		puts "INFO: remove $DESIGN_LIBRARY"
		file delete -force $DESIGN_LIBRARY
}

set init_verilog        $VERILOG_NETLIST_FILES
set init_mmmc_file      $VIEWDEFINATION_FILE
set init_top_cell       $DESIGN_NAME
set init_gnd_net        $GND_NET
set init_pwr_net        $PWR_NET
set init_lef_file       "$TECH_LEF_FILE $STD_LEF_FILE $MACRO_LEF_FILE"

set init_design_uniquify 1
set init_remove_assigns 1

file delete -force ${DESIGN_LIBRARY}
file mkdir ${DESIGN_LIBRARY}

init_design

############################
# PG connection
# ##########################
source -e -v user_scripts/pg_connection.tcl


#####################################
# Post-init_design customizations
# ##################################
if {[file exists $POST_SCRIPT($current_step)]}  {
		puts "INFO: Sourcing $POST_SCRIPT($current_step)"
		source $POST_SCRIPT($current_step)
} else {
		puts "WARN: $POST_SCRIPT($current_step) not exist. Skip to source it."
}


saveDesign ${DESIGN_LIBRARY}/${DESIGN_NAME}.${current_step}


###################################################
# Report
# ##############################################
if {$REPORT_QOR($current_step)} {
		source -e ./user_scripts/report_qor.tcl
} else {
		puts "INFO: Skip report for step: $current_step"
}

date > ${current_step}

exit






